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1/18 st50160 september 2004 1 general features wan modem feature set embedded adsl transceiver ansi t1.413, itu g.dmt annex a, b, c and deutsche telecom ur-2 compliant, splitterless itu g.lite compatibility: ? mtc20174, adsl front end, 7th generation, integrated line driver, dcxo 1.1 session control pppoe point to point protocol over ethernet pppoa point to point protocol over atm pppoa relay via ppp session control on terminal 1.2 atm features adaptation layers: aal5 (data), supported in hardware encapsulation: rfc1483 and rfc2684, multi protocol encapsulation over atm aal5 bridged and routed modes atm circuit: 8 pvc data qos: ubr, vbr, cbr 1.3 lan feature set 1 ethernet 10/100 (r)mii port (hpna compatible) 1 usb port (bridged with lan/wlan port) wireless support with reverse mii port 2 uarts, bluetooth compatible bridging: ieee 801.1d, spanning tree wan to lan on ethernet or usb embedded router: rip1, rip2, static routing nat/pat with extended alg support dhcp server/client ip protocol: tcp/ip arp sharing access, igmp, icmp support up to 128 stations embedded http server for configuration 1.4 configuration and provisioning configuration: remote configuration via java? enabled browser firmware remote upload via network. management: snmp, uni3.1, ilmi 4.0 (management and auto configuration) 1.5 customization customization with comprehensive api development tool based on windows environment on pc posix compatible rtos exposed bsp layer flexible development licenses based on kernel software in object or source format 2applications low cost adsl residential gateway (rg) residential gateway with broadband adsl wan transceiver wan to lan bridge and router with adsl wan transceiver and ethernet mii wireless lan access point with adsl wan transceiver and ethernet mii adsl wan to usb bridge dual ethernet/usb bridge with bridged our routed wan adsl transceiver data brief adsl residential combo gateway processor fi gure 1. p ac k age table 1. order codes part number description ST50160PF lbga208 (17x17x1.7mm) lbga208 (17x17x1.7mm) rev. 1
st50160 2/18 3 description the st50160 is a low cost adsl bridge and lan router. one 10/100mbits ethernet port allows the con- nection of a lan to the wan in bridged or routed mode. the data traffic can be routed through a local terminal by using the lan /wlan port or the usb port. the presence of nat and dhcp and the api slots for firewall functions allow for a high-speed connection of lan connected devices like pc to the public internet in an isolated and secure environment. the chip is built around an arm 946es risc processor. it embeds an adsl, a complete adsl transceiver and multiple lan interfaces allowing multiple medium exploitation. the data traffic can be routed through a local terminal by using the lan/wlan ports or the usb port. a comprehensive software package is available with the soc solution. the solution has been developed with the customization in mind. several software license plans are proposed as well as a user friendly development environment. figure 2. block diagram arm946es core + cache rom 128x32 ahb-apb bridge ahb 32 bit sdram controller aal5 ahb master aal5 ahb slave apb peripherals cleandmep ahb aal5 sar jennic sachemc-ip core utopia l2 analog pll ahb 32 bit dpram 4x4k udc-ahb dma master/slave reverse mii i/f usb transceiver tcm port ethernet ahb master ahb target interface slave packet engine ethernet mac ethernet dma controller uart bt learning bridge filter usb1.1 spi i/f isa cross bar
3/18 st50160 4 hardware description the st50160 processor combines a dynamite? adsl transceiver with a dedicated arm946es risc processor. in order to maintain high data throughput, a16kbyte cache memory for program and a 16kbyte memory for data are attached to the risc processor. the processing of most of the layer 2 protocols on the atm (sar and aal) and ip (mac filter and bridge) sides are performed by specific hardware blocks, relieving the processors from these tasks. the chip provides minimal external components and maximum flexibility. the chip contains one ethernet 10/100 base-t mac. the exposed mii interface allows the con- nection to alternate lan mediums like hpna and hplug. a usb interface allows an easy serial connec- tion. the usb port is bridged with the ethernet mac. a specific interface allow the connection of wireless lan transceiver line 802.11b, wifi. the st50160 device is targeted for low-cost residential gateway. its primary design goal is to minimize cost. secondary design goals are: ? low system cost solution (reduced bom, optimized soc technology) ? low power to facilitate primary service capabilities and thermal system issues ? low emi to simplify packaging and qualification of systems. 4.1 hardware features ? arm 946es risc processor dedicated to network processing, api and dsl modem control ? hardware atm processor: sar function with aal5 processing. ? hardware packet processor: ethernet mac, learning and filter bridge. ? one 10/100 base-t ethernet macs with mii interface for external phy or multi port switch ? one usb port v1.1 compatible (glue-less interface to external transceiver) ? one 802.11b wireless lan interface. ? one serial or 8(*) or 16(*) bit wide flash port, isa compatible. up to 16mbyte addressable memory. (*) packaging option. ? one 32 bit wide sdram interface with 32mbyte addressable memory. ? interface to dynamite? adsl analog front end (afe) chip mtc20174. ? multi channel dma engine integrated with peripherals ? low power: 1.8v +/-10% core voltage, 3.3v +/- 10% i/o voltage ? 128 instructions (32 bits) of boot rom ? gpio with support for led ? cc-based multi ice/compiler support with assembler and debugger ? software chip and system simulators for software development and debug ? jtag board-level test interface ? 140mhz system clock (processor cycle clock) ? sleep mode with wake on lan wake on wan feature ? programmable system frequency clock: 140, 105, 70, 35 and 129mhz (fall back mode). 5 software architecture the software is organized in 5 clusters. ? user interface api ?system services ?network services ? tcp/ip socket ? atm encapsulation ? atm drivers a description of the clusters contents is given in the software features section
st50160 4/18 figure 3. embedded software block diagram 6 software development environment the st50160 presents a comprehensive set of software features. in order to allow manufacturer to cus- tomize further the system, a set of api functions are made available. the exploitation of the api functions requires the acquisition of a development environment. the development environment is based on the el- ements depicted hereunder. ? arm developer suite (ads) v1.1 or higher ? ati development license ? ati ede (embedded development environment) ? ms developer studio (vc++) v6.0 or higher along with the development environment a number of specific tools are provided to allow the diagnostic and the downloading operation of the executable on the nonvolatile memory attached to the st50160. ip socket tcp mac utopia master driver bridging, spanning learning tree aal5 / sar mii driver bridge firmware udp udp atm encapsulation user interface api bridge router add-on ro u t e r rip1.2 dhcp nat ras pppoe pppoa pptp network services http srv snmp tftp dns system services download ctrl-e mib rtos flash mgr ilmi uni3.1 diagnostic firewall network isolation
5/18 st50160 7 nominal characteristics the st50160 processor is available in a 208-pin lbga (plastic ball grid array) package. all i/os are 3.3v cmos levels, with all inputs and 3-states having 5v tolerance. no pins have internal pull-ups and pull- downs. 8 application example the following example shows the reference design developed for the evaluation board. it is a complete adsl-based data gateway kit connecting to an adsl enabled phone jack and provides a connection to a 10/100bt ethernet port. it utilizes a set of 2 assp available from st. the st50160 is composed of the following elements: a dynamite? adsl modem afe (mtc2074). ad- ditional components are sdram and flash memory. discrete components and connectors are not shown on the block diagram. larger sdram can be connected to the st50160 to store and execute additional (custom) application. figure 4. application block diagram intensive qualification efforts have been spent on this reference design insuring users of the platform max- imum interoperability and smooth, rapid design-in, hence reducing engineering effort and total time to market (ttm). supply - typical power supply voltage 1.8v - typical pad power supply voltage 3.3v threshold - input low voltage -0.5v -1.0v - input high voltage 2.3v- 5.5v consumption - core consumption: 1400mw. reduced power mode available. environment - commercial grade: 0c - 70c (32f ? 158f) - industrial grade: -45c - 85c. (-49f - 185f) packages - 208-pin plastic bga package (8/16 bus flash) technology - cmos 0.18 micron mtc-50150 mtc-20174 flash adsl afe w a n st50160 802.11b wifi board l a n sdram ste101 ethernet phy interface logic
st50160 6/18 table 2. pin list name pin bga 208 b buffer type description sdram interface ( 57) sd_nras n2 o prt08dgz sdram row address strobe sd_clk p2 b prb08dgz sdram clock sd_ncas n1 o prt08dgz sdram column address strobe sd_nwe n3 o prt08dgz sdram write strobe sd_d31 / fs clk #16 r8 bd prdw08dgz sdram data bit 31 / full scan clock #16 sd_d30 / fs clk #17 t8 bd prdw08dgz sdram data bit 30 / full scan clock #17 sd_d29 / fs_in #16 p8 bd prdw08dgz sdram data bit 29 / full scan input #16 sd_d28 n8 bd prdw08dgz sdram data bit 28 sd_d27 t9 bd prdw08dgz sdram data bit 27 sd_d26 r9 bd prdw08dgz sdram data bit 26 sd_d25 n10 bd prdw08dgz sdram data bit 25 sd_d24 p10 bd prdw08dgz sdram data bit 24 sd_d23 t10 bd prdw08dgz sdram data bit 23 sd_d22 t11 bd prdw08dgz sdram data bit 22 sd_d21 r11 bd prdw08dgz sdram data bit 21 sd_d20 n12 bd prdw08dgz sdram data bit 20 sd_d19 p12 bd prdw08dgz sdram data bit 19 sd_d18 t12 bd prdw08dgz sdram data bit 18 sd_d17 r12 bd prdw08dgz sdram data bit 17 sd_d16 p13 bd prdw08dgz sdram data bit 16 sd_a0 t7 o prt08dgz sdram address bit 00 sd_a1 n6 o prt08dgz sdram address bit 01 sd_a2 p6 o prt08dgz sdram address bit 02 sd_a3 t6 o prt08dgz sdram address bit 03 sd_a4 r6 o prt08dgz sdram address bit 04 sd_a5 t5 o prt08dgz sdram address bit 05 sd_a6 r5 o prt08dgz sdram address bit 06 sd_a7 n4 o prt08dgz sdram address bit 07 sd_a8 t4 o prt08dgz sdram address bit 08 sd_a9 p4 o prt08dgz sdram address bit 09 sd_a10 r4 o prt08dgz sdram address bit 10 sd_a11 t3 o prt08dgz sdram address bit 11 sd_a12 r3 o prt08dgz sdram address bit 12 sd_a13 t2 o prt08dgz sdram address bit 13 sd_a14 t1 o prt08dgz sdram address bit 14 sd_d15 g1 bd prdw08dgz sdram data bit 15 sd_d14 g3 bd prdw08dgz sdram data bit 14 sd_d13 g4 bd prdw08dgz sdram data bit 13 sd_d12 h2 bd prdw08dgz sdram data bit 12 sd_d11 h1 bd prdw08dgz sdram data bit 11
7/18 st50160 sd_d10 h3 bd prdw08dgz sdram data bit 10 sd_d9 h4 bd prdw08dgz sdram data bit 09 sd_d8 j4 bd prdw08dgz sdram data bit 08 sd_d7 j2 bd prdw08dgz sdram data bit 07 sd_d6 k4 bd prdw08dgz sdram data bit 06 sd_d5 k3 bd prdw08dgz sdram data bit 05 sd_d4 k1 bd prdw08dgz sdram data bit 04 sd_d3 l4 bd prdw08dgz sdram data bit 03 sd_d2 l3 bd prdw08dgz sdram data bit 02 sd_d1 l1 bd prdw08dgz sdram data bit 01 sd_d0 l2 bd prdw08dgz sdram data bit 00 sd_ncs p1 o prt08dgz sdram chip select sd_cke r1 o prt08dgz sdram clock enable sd_dqm0 m1 o prt08dgz sdram data mask 0 (byte enable) sd_dqm1 m2 o prt08dgz sdram data mask 1 (byte enable) sd_dqm2 p7 o prt08dgz sdram data mask 2 (byte enable) sd_dqm3 n7 o prt08dgz sdram data mask 3 (byte enable) arm/miscellaneous interface (3) armdebug b7 i pdidgz arm debug test mode (multiplexes the arm tap onto the jtag pins) tied to ?0? in functional mode (jtag tap mode) input with pad monitor only (jtag compliancy pin) flashboot / pll_ctr_run / fs clk #1 a7 i / i / i pdidgz boot from external parallel flash prom (isa) rather than from internal rom (uart or spi) / starts/stops the pll test counter tied to ?1? in functional mode full scan clock #1 input with bs only bypasspll / fs in #1 c5 i / i pdidgz bypass cpu clock generation pll tied to ?0? in functional mode full scan input #1 with bs and padmonitor jtag/test interface (5) tck e3 iu pduwdgz boundary scantest clock tdi f3 iu pduwdgz boundary scan test data in tdo e1 oz prt08dgz boundary scan test data out tms e4 iu pduwdgz boundary scan test mode shift ntrst f4 id pddwdgz boundary scan reset adsl interface (13) af_rxd3 / fs clk #2 b1 i / i pdidgz adsl afe receive data bit 3 / full scan clock #2 af_rxd2 / fs clk #3 a1 i / i pdidgz adsl afe receive data bit 2 / full scan clock #3 af_rxd1 / fs clk #4 a2 i / i pdidgz adsl afe receive data bit 1 / full scan clock #4 af_rxd0 / fs clk #5 b3 i / i pdidgz adsl afe receive data bit 0 / full scan clock #5 table 2. pin list (continued) name pin bga 208 b buffer type description
st50160 8/18 af_txd3 / fs out #11 e2 o / o prt08dgz adsl afe transmit data bit 3 / full scan out #11 af_txd2 / fs out #12 d4 o / o prt08dgz adsl afe transmit data bit 2 / full scan out #12 af_txd1 / fs out #13 d1 o / o prt08dgz adsl afe transmit data bit 1 / full scan out #13 af_txd0 / fs out #14 d3 o / o prt08dgz adsl afe transmit data bit 0 / full scan out #14 af_clwd / fs clk #6 c1 i / i pdidgz adsl start of word indication / full scan clock #6 af_ctrldata / fs out #16 c2 o / o prt08dgz adsl serial data transmit channel / full scan out #16 mclk b4 is pdisdgz adsl master clock mnrst a3 is pdisdgz adsl master (chip) reset af_npowerlow/ fs out #15 d2 o / o prt08dgz adsl power down analog frontend (active high) / full scan out #15 ethernet mii/reverse mii interface (18) m_txclk p15 is pdisdgz mii transmit clock m_txen / fs out #9 pll_div_out t14 o / o prt08dgz mii / reverse mii transmit enable / full scan out #9 / divided clock in pll test mode m_txd3 / fs out #8 r14 o / o prt08dgz mii / reverse mii transmit data bit 3 / full scan out #8 m_txd2 / fs out #7 t15 o / o prt08dgz mii / reverse mii transmit data bit 2 / full scan out #7 m_txd1 / fs out #6 t16 o / o prt08dgz mii / reverse mii transmit data bit 1 / full scan out #6 m_txd0 / fs out #5 r16 o / o prt08dgz mii / reverse mii transmit data bit 0 / full scan out #5 m_txer / fs out #10 pll_nom_out t13 o / o prt08dgz mii / reverse mii transmit error / full scan out #10 / pll output clock in pll test mode m_crs/ fs_in #15 m14 bd id prdw08dgz mii / reverse mii carrier sense / full scan input #15 m_col / fs in #14 m13 bd id prdw08dgz mii / reverse mii collision detection / full scan input #14 m_rxclk n15 is pdisdgz mii receive clock m_rxdv / fs clk #7 p16 i / i pdidgz mii / reverse mii receive data valid / full scan clock #7 m_rxd3 / fs clk #8 n14 i / i pdidgz mii / reverse mii receive data bit 3 / full scan clock #8 m_rxd2 / fs clk #9 n16 i / i pdidgz mii / reverse mii receive data bit 2 / full scan clock #9 m_rxd1 / fs clk #10 n13 i / i pdidgz mii / reverse mii receive data bit 1 / full scan clock #10 m_rxd0 / fs clk #11 m15 i / i pdidgz mii / reverse mii receive data bit 0 / full scan clock #11 m_rxer / fs clk #12 m16 i / i pdidgz mii / reverse mii receive error / full scan clock #12 table 2. pin list (continued) name pin bga 208 b buffer type description
9/18 st50160 m_mdc l14 b prb08dgz mii / reverse mii management clock m_mdio / fs in #13 l13 b / i prb08dgz mii / reverse mii management data / full scan input #13 external pull down resistor of 2 k is required gpio interface (11) gpio10 / fcs2 / -bd o prdw08dgz general purpose pin 10 / serial flash chip select #2 / gpio9 / - bd/ prdw08dgz general purpose pin 9 / gpio8 / - bu/ i pruw08dgz general purpose pin 8 / boot from uart or spi gpio7 / - bu / i pruw08dgz general purpose pin 7 / boot from uart or spi gpio6 / ser2si / fs in #6 h16 b / i / o / i prb08dgz general purpose pin 6 / cleandmep serial interface 2 ? serial input / isa-like interface reset output full scan input #6 gpio5 / ser2so / fs in #7 h14 b / o / i / i prb08dgz general purpose pin 5 / cleandmep serial interface 2 ? serial output / restore defaults/version select input full scan input #7 gpio4 / m_link/ fs in #8 f16 b / i / i / i prb08dgz general purpose pin 4 / ethernet link status input / isa-like interface ireq# full scan input #8 gpio3 / pb1/ fs in #9 f14 b / o / i / i prb08dgz general purpose pin 3 / main clock control pb1 / dying gasp interrupt input / full scan input #9 gpio2 / pb0 / fs in #10 a13 b / o / o / i prb08dgz general purpose pin 2 / main clock control pb0 / software reset ouput / full scan input #10 gpio1 / si_rclk / ser2ncts/ fs in #11 f13 b / i / i / i prb08dgz general purpose pin 1 / external uart (bt) clock / cleandmep serial interface 2 nrts / full scan input #11 gpio0 / ser2nrts / fs in #12 g16 b / o / o / i prb08dgz general purpose pin 0 / isa-like interface a6 cleandmep serial interface 2 ncts / full scan input #12 spi (serial flash interface) (4) spi_cs \ - o / prt08dgz flash chip select #1 spi_clk / - o / prt08dgz spi clock spi_txd / - o / prt08dgz spi transmit data (to serial flash) spi_rxd / - id / pddwdgz spi receive data (from serial flash) uart1/uart_bt si serial interface (4) si_sin / ser1si / fs clk #14 c7 i / i pdidgz serial interface serial data input / cleandmep serial interface 1 ? serial input / full scan clock #14 table 2. pin list (continued) name pin bga 208 b buffer type description
st50160 10/18 si_sout / ser1so b8 o prt08dgz serial interface serial data output / andtree output cleandmep serial interface 1 ? serial output si_nrts / ser1nrts / fs out #1 a8 o / o prt08dgz serial interface not ready to send / cleandmep serial interface 1 nrts / full scan output #1 si_ncts / ser1ncts / fs clk #15 d7 i / i pdidgz serial interface not clear to send / cleandmep serial interface 1 ncts / full scan clock #15 isa-like interface (42) isa_ncs h15 o prt08dgz isa bus chip select / address enable with bs - deactivated by nsel_isa isa_nrd / fs out #4 b13 o prt08dgz isa bus read strobe / output enable with bs - deactivated by nsel_isa / full scan out #4 isa_nwr / fs out #3 c13 o prt08dgz isa bus write strobe with bs - deactivated by nsel_isa / full scan out #3 rom_ncs / fs out #2 a14 o prt08dgz flash prom chip select / address enable with bs - deactivated by nsel_isa / full scan out #2 rom_addr21 d14 o prt08dgz flash prom address bit 21 with bs - deactivated by nsel_isa rom_addr20 e15 o prt08dgz flash prom address bit 20 with bs - deactivated by nsel_isa rom_addr19 e16 o prt08dgz flash prom address bit 19 with bs - deactivated by nsel_isa rom_addr18 e14 o prt08dgz flash prom address bit 18 with bs - deactivated by nsel_isa rom_addr17 g14 o prt08dgz flash prom address bit 17 with bs - deactivated by nsel_isa rom_addr16 g13 o prt08dgz flash prom address bit 16 with bs - deactivated by nsel_isa rom_addr15 d13 o prt08dgz flash prom address bit 15 with bs - deactivated by nsel_isa rom_addr14 b12 o prt08dgz flash prom address bit 14 with bs - deactivated by nsel_isa rom_addr13 a12 o prt08dgz flash prom address bit 13 with bs - deactivated by nsel_isa rom_addr12 c12 o prt08dgz flash prom address bit 12 with bs - deactivated by nsel_isa rom_addr11 a11 o prt08dgz flash prom address bit 11 with bs - deactivated by nsel_isa rom_addr10 c11 o prt08dgz flash prom address bit 10 with bs - deactivated by nsel_isa rom_addr9 b10 o prt08dgz flash prom address bit 9 with bs - deactivated by nsel_isa rom_addr8 a10 o prt08dgz flash prom address bit 8 with bs - deactivated by nsel_isa table 2. pin list (continued) name pin bga 208 b buffer type description
11/18 st50160 rom_addr7 c10 o prt08dgz flash prom address bit 7 with bs - deactivated by nsel_isa rom_addr6 d10 o prt08dgz flash prom address bit 6 with bs - deactivated by nsel_isa rom_addr5 a9 o prt08dgz flash prom address bit 5 with bs - deactivated by nsel_isa isa_addr4 / rom_addr4 b9 o prt08dgz isa / flash prom address bit 4 with bs - deactivated by nsel_isa isa_addr3 / rom_addr3 c9 o / o prt08dgz isa / flash prom address bit 3 with bs - deactivated by nsel_isa isa_addr2 / rom_addr2 d9 o / o prt08dgz isa / flash prom address bit 2 with bs - deactivated by nsel_isa isa_addr1 / rom_addr1 d8 o / o prt08dgz isa / flash prom address bit 1 with bs - deactivated by nsel_isa isa_addr0 / rom_addr0 c8 o / o prt08dgz isa / flash prom address bit 0 with bs - deactivated by nsel_isa isa_data15 / rom_addr23 h13 bd/ o prdw08dgz isa / flash prom data bus bit 15 / flash prom address bit 23 in 8 bit mode with bs&andtree - deactivated by nsel_isa isa_data14 / rom_addr22 j13 bd/ o prdw08dgz isa / flash prom data bus bit 14 / flash prom address bit 22 in 8 bit mode/ with bs&andtree - deactivated by nsel_isa isa_data13 - bd prdw08dgz isa / flash prom data bus bit 13 with bs&andtree - activated by sel_isa16 when nsel_isa active isa_data12 - bd prdw08dgz isa / flash prom data bus bit 12 with bs&andtree - activated by sel_isa16 when nsel_isa active isa_data11 - bd prdw08dgz isa / flash prom data bus bit 11 with bs&andtree - activated by sel_isa16 when nsel_isa active isa_data10 - bd prdw08dgz isa / flash prom data bus bit 10 with bs&andtree - activated by sel_isa16 when nsel_isa active isa_data9 - bd prdw08dgz isa / flash prom data bus bit 9 with bs&andtree - activated by sel_isa16 isa_data8 - bd prdw08dgz isa / flash prom data bus bit 8 with bs&andtree - activated by sel_isa16 isa_data7 b14 bd prdw08dgz isa / flash prom data bus bit 7 with bs&andtree - deactivated by nsel_isa isa_data6 / a15 bd prdw08dgz isa / flash prom data bus bit 6 with bs&andtree - deactivated by nsel_isa isa_data5 / a16 bd prdw08dgz isa / flash prom data bus bit 5 with bs&andtree - deactivated by nsel_isa isa_data4 / fs in #2 b16 bd prdw08dgz isa / flash prom data bus bit 4 with bs&andtree - deactivated by nsel_isa full scan input #2 isa_data3 / fs in #3 c15 bd prdw08dgz isa / flash prom data bus bit 3 with bs&andtree - deactivated by nsel_isa full scan input #3 table 2. pin list (continued) name pin bga 208 b buffer type description
st50160 12/18 isa_data2 / fs in #4 c16 bd prdw08dgz isa / flash prom data bus bit 2 with bs&andtree - deactivated by nsel_isa full scan input #4 isa_data1 / fs in #5 d16 bd prdw08dgz isa / flash prom data bus bit 1 with bs&andtree - deactivated by nsel_isa full scan input #5 isa_data0 / fs clk #13 d15 bd prdw08dgz isa / flash prom data bus bit 0 with bs&andtree - deactivated by nsel_isa full scan clock #13 usb interface (5) usb_dp j15 b pusbf11dg usb data + usb_dm j16 b usb data - usb_clk j14 is pdisdgz 48 mhz udc input clock vdd_an_usb k14 p pvdd6dg 3.3v (auvdd) vss_an_usb k13 p pvss6dg 0 v (not common with vss_core or vss_io) (auvss) miscellaneous test pins (4) iddqmode c6 i pdidgz iddq mode activation with padmonitor only (jtag compliancy pin) fsshift a6 id pddwdgz full scan shift enable with padmonitor only (jtag compliancy pin) select106m - id pddwdgz activates 106 mhz cpu clock if connected to ?1?, with padmonitor only (jtag compliancy pin) select70m - id pddwdgz activates 70 mhz cpu clock if connected to ?1?, with padmonitor only (jtag compliancy pin) core power supply pins (26) [1.8v] vdd_core f2 k2 r2 p5 n9 r10 r15 l15 e13 b15 d12 b6 b2 p pvdd1dgz 1.8v (vdd) vss_core f1 n5 p9 k10 l16 f15 g10 b11 d5 g9 h9 j10 h10 p pvss3dgz 0 v, common with vss_io (vss) table 2. pin list (continued) name pin bga 208 b buffer type description
13/18 st50160 i/o power supply pins (26) [3.3v] vdd_io c3 g2 j3 m3 p3 r7 n11 p14 k15 g15 c14 d11 d6 k16 p pvdd2dgz 3.3 v (vd33) vss_io h8 h7 j1 m4 k7 k8 p11 j9 g8 g7 j7 j8 k9 r13 p pvss3dgz 0 v, common with vss_core (vss) pll digital and analog power supply pins (4) [1.8v] vdd_dig_pll a5 p pvdd1p pvdd5p 1.8v (dvdd) vss_dig_pll b5 p pvss1p pvss5p 0 v (not common with vss_core or vss_io) (dvss) vdd_an_pll a4 p pvdd1p 1.8v (avdd) vss_an_pll c4 p pvss1p 0 v (not common with vss_core or vss_io) (avss) unconnected pads with an internal pull-down resistor swmode0 - id pddwdgz do not bond; ?0? default value, bond to nearby vdd_io to get ?1? value (allow sw to differentiate between bridge/router mode) input with pad monitor only selrstdly - id pddwdgz do not bond; ?0? default value; bond to nearby vdd_io to get ?1? value (activates prolonged external reset delay) input with pad monitor only sel_c184 - id pddwdgz do not bond; ?0? default value, bond to nearby vdd_io to get ?1? value (activates ios & test logic for c184 support) input with pad monitor only table 2. pin list (continued) name pin bga 208 b buffer type description
st50160 14/18 nsel_isa - id pddwdgz do not bond ?0? default value; activates ios & test logic for 8 bit parallel flash support bond to nearby vdd_io (k14) in bga180 desactivates ios & test logic for parallel flash support input with pad monitor only sel_isa16 - id pddwdgz do not bond; ?0? default value; bond to nearby vdd_io to get ?1? value (activates ios & test logic for 16 bit parallel flash support when nsel_isa is not bonded). this feature might be activates for higher pincount package (256bga). input with pad monitor only sel_spi - id pddwdgz do not bond ?0? default value; desactivates ios & test logic for serial flash support bond to nearby vdd_io (b13) in bga180 activates ios & test logic for serial flash support input with pad monitor only af_rxd4 - id pddwdgz adsl afe receive data bit4 with bs&andtree - activated by sel_c184 af_rxd5 - id pddwdgz adsl afe receive data bit5 with bs&andtree - activated by sel_c184 af_rxd6 - id pddwdgz adsl afe receive data bit6 with bs&andtree - activated by sel_c184 af_rxd7 - id pddwdgz adsl afe receive data bit7 with bs&andtree - activated by sel_c184 af_rxd8 - id pddwdgz adsl afe receive data bit8 with bs&andtree - activated by sel_c184 af_rxd9 - id pddwdgz adsl afe receive data bit9 with bs&andtree - activated by sel_c184 af_ctrldata_in - id pddwdgz adsl serial data receive channel with bs&andtree - activated by sel_c184 table 2. pin list (continued) name pin bga 208 b buffer type description
15/18 st50160 figure 5.
st50160 16/18 figure 6. lbga208 (17x17x1.7mm) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.210 1.700 0.048 0.067 a1 0.270 0.011 a2 1.120 0.044 b 0.450 0.500 0.550 0.018 0.020 0.022 d 16.80 17.00 17.20 0.661 0.669 0.677 d1 15.00 0.590 e 16.80 17.00 17.20 0.661 0.669 0.677 e1 15.00 0.590 e 0.90 1.00 1.10 0.035 0.039 0.043 f 0.75 1.00 1.250 0.029 0.039 0.049 ddd 0.200 0.008 lbga208 (17x17x1.70) low profile ball grid array 1 a b c d e f g h j k l m n p r t 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bottom view a1 corner index area (see note 1) seating plane e ee1 d d1 f a a2 a1 ?b (208 balls) ddd c c lbga208m note 1 - the terminal a1 corner must be identified onthe top surface by using a corner chamfer, ink or metallized markings, or other f eature of package body or integral heatslug. - a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. - exact shape of each corner is optional. 7184626b
17/18 st50160 table 3. revision history date revision description of changes september 2004 1 first issue in edocs dms.
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 18/18 st50160

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